1. Field of the Invention
The present invention relates generally to storage controller systems, and more particularly to a hardware mechanism for managing cache structures in a storage controller system.
2. Description of Related Art
Host computer systems often connect to one or more storage controllers that provide access to an array of storage disks. A host system requests access to data at a virtual disk location, and a storage controller accesses a corresponding physical storage location on one of the storage disks and provides access to the data by the host system. Typically, a storage controller includes one or more microprocessors that communicate the data between the storage disk and the host system.
A common feature of a storage controller system is disk caching, which involves temporarily storing contiguous regions of data from a storage disk to a cache memory unit. It is to be understood that accesses to a memory unit typically complete much more quickly than accesses to a storage disk. To access a storage location, a storage system microprocessor will specify a physical storage location on the storage disk. However, instead of retrieving only the specified storage location, the microprocessor will also retrieve (i.e., "prefetch") a subsequent, sequential portion of the storage disk, loading it into the cache memory. The reasoning behind this caching of sequential data from the storage disk is that storage disk accesses are most likely sequential in nature. Therefore, it is probable that the next access by the microprocessor will be to the next sequential storage location on the storage disk, which has already been loaded into the cache memory during the prefetch. When the requested data is found in a cache memory, it is referred to as a "cache hit." In contrast, when the requested data in not found in the cache memory, it is referred to as a "cache miss". A cache miss requires that the storage control system perform the normal retrieval of the requested data from the disk array. As a result, the microprocessor in the storage controller can, with a cache hit, avoid the time-consuming access to the next storage location on the storage disk, and instead quickly access the data in the cache memory and return it to the microprocessor. In most circumstances, disk caching results in increased performance of the data storage system.
One method of identifying a storage location is called Logical Block Addressing (LBA). LBA is an addressing scheme to overcome a 528 megabyte limit imposed on the current addressing standard for an IDE (Integrated Disk Electronics) disk drive. Effectively, LBA is used with SCSI and IDE disk drives to translate specified cylinder, head, and sector parameters of the disk drive into addresses that can be used by an enhanced BIOS to access the disk drive. In SCSI systems, a Logical Unit Number (LUN) is preferably combined with the LBA address to constitute a storage location identifier. Alternative addressing schemes employing storage location identifies also exist, including ECHS (Extended Cylinder, Head, Sector addressing), "Large", and "Big IDE" addressing.
Typically, a storage processor manages a disk cache by manipulating cache structures in main memory. However, the operations of inserting, deleting, and searching cached elements are highly processor-intensive and divert processing power from other functions of the storage control system. Furthermore, cache management relies heavily on memory access to manipulate the cache structures and, therefore, can consume a significant amount of processor bus bandwidth if managed by the storage processor in processor memory. Also, manipulation of the cache management structures by the storage processor can dilute the storage processor's first and second level caches. A need exists for a high performance cache management state machine capable of reducing the impact of cache management on the storage processor, processor memory bus, and processor caches.